This invention pertains generally to the field of computer system power management, and more particularly to a distributed power management system and method wherein power management functions are delegated to individual modular subsystems or functional components within the overall computer system.
Power management has been, and continues to be, a major concern in the development and implementation of battery powered or battery operated microprocessor based systems, such as laptop computers, notebook computers, palmtop computers, personal data assistants (PDAs), hand-held communication devices, wireless telephones, and any other devices incorporating microprocessors in a battery-powered unit, including units that are occasionally battery powered, but that also operate from a power line (AC) source. The need for power management is particularly acute for battery-operated single-chip microcomputer systems, where the desirability or requirement for overall reduction in physical size (and/or weight) also imposes severe limits on the size and capacity of the battery system, and yet where extending unit operating time without sacrificing performance is a competing requirement. Conventional methods for power managing these types of systems have typically been based on a centralized power management unit architecture.
For example, in an exemplary conventional centralized power management unit 20, such as that illustrated in FIG. 1, an activity monitor 21, monitors accesses to specific system resources, such as access to serial ports 31, parallel ports 32, a display subsystem controller 33, memory controller 34, keyboard controller 35, and like resources. Such activity monitor 21 may be implemented in hardware or software, and in either case may be configured (such as by hard wiring, firmware, or software) to accommodate specification of a particular system resource address range or ranges to be monitored. The centralized power management unit (PMU) passively watches activity on the bus concerning other system resource units. The occurrence of one or more pre-identified addresses or address ranges on address bus 26 is recognized by the activity monitor, which in turn operates to trigger a particular predetermined action, such as to alter the operating state or mode of one or more system devices to affect a change in the power consumption state of the system.
In one conventional power management system, five operating states are provided: ON, DOZE, SLEEP, SUSPEND, and OFF. These names are not uniformly standardized, but each of the DOZE, SLEEP, and SUSPEND modes represents intermediate power consumption states between fully ON and fully OFF. By way of example, under one set of rules, in the ON state, the bus clock may operate at full speed, the LCD display system may be ON, memory may be ON, and the system as a whole may be ON. In the DOZE state, the bus clock may be slowed or stopped, the LCD is ON, memory is ON, and the system is ON. The SLEEP state provides a bus clock which is either slow or stopped, as compared to the full speed bus clock, the liquid crystal display is OFF, memory remains ON, and the system as a whole remains ON and responsive. In the SUSPEND state, the bus clock is typically stopped, the liquid crystal display is OFF, memory is ON, but the system as a whole is OFF. Maintaining memory in the ON state is important for rapid resumption of processing, such as when a keyboard key is struck by a user to reinitiate input processing on the computer system. Finally, in the OFF state, the bus clock is stopped and the subsystem power supply to the LCD, memory, and system are OFF.
Other conventional centralized power management systems may implement more or fewer states or power consumption modes, and such systems may control power delivery to devices and/or modify clock frequency.
Activity masks 22 may also be provided, and, when present, permit control of which of the monitored system resources will generate an activity indicator when accessed. Such activity indicators are used to control transitions of the computer from one state to another, such as, for example, in the context of the exemplary system described above, a transition from SLEEP state to the DOZE state, or the ON state, in response to a user of the computer making a keyboard key entry. When activity masks are implemented, those resources which are to be monitored for activity are unmasked, and those resources which may be ignored and are not monitored are masked. Some implementations provide a unique activity mask for each power management state.
Activity timers 23 may also be provided. The activity timers are typically initialized by software to specify the amount of xe2x80x9cidlexe2x80x9d time which may be allowed to elapse before moving to the next (typically lower) power consumption state. The value of the idle time may typically vary for each power state or state transition, but tends to be defined as the following order of magnitude timings: a power state transition from ON to DOZE is implemented with a first idle time of between about 1 millisecond (1xc3x9710xe2x88x923 seconds) and some small number of seconds, for example, from about 1 to about 30 seconds. The transition from a DOZE state to a SLEEP state is typically implemented with a second idle time of seconds to one or a few minutes. And, the power state transition from SLEEP to SUSPEND state is typically implemented with a third idle time of a few minutes to several minutes. U.S. Pat. No. 5,396,635 herein incorporated by reference, includes a description of one particular power management system which has an activity monitor, and uses activity masks and activity timers.
Note that for a microprocessor operating at 200 MHZ, each clock cycle represents 5.0 nanoseconds (5xc3x9710xe2x88x929 sec), and for a system bus operating at a 100 MHZ clock, each clock cycle represents 10 nanoseconds. Furthermore, it is noted that external memory access typically requires 40-60 nanoseconds, while internal memory may operate at the microprocessor clock rate. It is therefore easily appreciated that even the shortest conventional idle period of, for example 1 millisecond, is long compared to a system bus cycle (10 nanoseconds) by a factor of 105.
In conventional computer power management systems, one activity timer, or timer value, is normally allocated per power management state. When unmasked activity is detected, the activity timer is reloaded or reset with the xe2x80x9ctime outxe2x80x9d timing value programmed by software. Then, when the activity timer for a particular power management state expires, either an interrupt is generated to allow software to control the transition to the next power management state, or the transition occurs automatically by hardware control.
Transition from a lower power consumption state to higher power consumption state may occur relatively more quickly. For example, the operating state may transition directly from the SUSPEND state upon detection of a single keyboard key entry to the ON state, or such change may require a plurality of events for such transition to occur.
With further reference to FIG. 1, the power state block 24 controls the system power management state and interfaces to the clock control logic 25. Clock control logic block 25 receives a clock input signal (clock_in) at a first clock frequency (f1) and controls the state of the output bus clock. Clock control 25 may pass the clock_in signal through, may slow the clock to a lower frequency (f2), or may stop the bus clock for the entire system during certain low power consumption power management states. State transitions can be initiated by software, or can occur automatically in hardware when an activity timer expires.
Centralized power management architecture, such as that exemplified by the system in FIG. 1, has the disadvantage that, when the system is operating in a reduced power consumption state, an access to any unmasked system resource typically causes an exit (state transition) from that reduced power state to a higher power consumption state, and, in the worst case, it transitions to a full xe2x80x9cONxe2x80x9d state independent of the access required. This transition may occur for all system resources independent of any actual requirement for participation by that resource at that time. Furthermore, since, in conventional systems, the finest timer resolution is typically controlled by the preset or programmed xe2x80x9cidlexe2x80x9d times which are measured and/or implemented in the millisecond or longer ranges, the computer system may need to wait unnecessarily to return to a lower power consumption or power saving state, even when access to a system resource is no longer required, or the required access cannot be made during a particular time interval due to multitasking constraints.
A further disadvantage from such conventional systems, is that system resource components receiving the bus clock continue to receive the bus clock signals at all times independent of any actual access to that resource, and that such signals are propagated to each and every component of the system. Because several hundred or several thousand gates are dynamically switching in response to the bus clock triggered transitions, independent of the actual access by the system of the resource, substantial power is consumed unnecessarily. This switching loss is particularly disadvantageous in current CMOS-based implementations where static operation has a much lower power consumption than dynamically switched operations.
Even for systems that may stop the bus clock propagation to certain devices during a very power conservative state (e.g. SUSPEND), propagation is typically either completely enabled or completely disabled, and when enabled, the clock propagates to all portions and circuits of each system resource without regard for functionality.
A further disadvantage of conventional systems which results in increased power consumption, pertains to the structure of the bus-to-device-interface interposed between a system bus and a particular system component.
A further disadvantage of conventional systems, particularly for software-based power management, is the delay associated with initiating access to a device which has been placed in a lower power consumption state. Once a device is placed in a reduced power consumption state, significant time delays (for example, delays on the order of tens of hundreds of micro seconds (10xe2x88x926 seconds) may be required to reconfigure the device for access.
In one aspect the invention, structure and method are provided for controlling and thereby reducing power consumption in a computer system having a bus and at least one device coupled to the bus without sacrificing computer performance or inhibiting a computer user""s rapid access to the computer. A unique identifier is associated with each device or resource associated with the computer, such as for example, memory, keyboard controller, mouse controller, input/output ports, and any other computer resource or peripheral. This unique identifier may typically be a device address or other device identifier such as a device serial number, network device address, and the like. Communications over a communications link such as a system or other parallel bus, serial bus, or wireless link, are monitored by each device for a predetermined time period to determine device identifiers communicated over communications link during that time period, and these identifiers (e.g. device addresses) are compared to the particular unique identifier associated or allocated to the monitoring device. Each device monitors the communications activity and is responsible for self-controlling its operating condition to minimize power consumption. Each device includes a first component which operates continuously so as to provide the monitoring functionality and a second component that operates in a low power consumption mode unless first component signals the second component that its operation is needed during that time period. The first component withholds a device operating input from the second component when none of the communicated identifiers match the particular device; and provide the device operating input to the second component when one of said communicated device identifiers match that particular device. The number of circuit components is reduced to a minimum in the first component so that the number of circuit elements which are continuously active are reduced. In one embodiment of the invention, the device operating input is a clock signal operating at the bus clock frequency. Power consumption is reduced due to the reduction in the number of circuits which are actively clocked. The inventive structure and method provide very fine temporal control of power consumption in the computer system.
In another aspect, the invention provides structure and method for a modular bus architectural (MBA) and fast modular bus architectural (FMBA) frames for System-on-a-Chip (SOC) designs including MBA/FMBA library modules that decrease design time. In another aspect, the invention provides structure and method for adjusting bus clock speed in accordance with bus activity and task performance requirements so that further control of power consumption in the system is achieved without sacrificing performance. In one embodiment, the clock rate is adjusted in accordance with preassigned performance factors associated either with a functional unit or with a task type so that the task completes within a desired time without unnecessary power consumption. In another aspect, the FMBA/MBA is provided with a configurable interface that provides alternative single-edge and double-edge First-In-First-Out buffers. Among other advantages, these FIFO structures permit interconnection of MBA/FMBA modules at the core logic level, MBA/FMBA block level, and chip level so that systems are readily and reliable designed and implemented with minimum redesign.